1. Field of the Invention
The embodiments of the invention generally relate to semiconductor device processing and, more specifically, to a method of forming planar and non-planar semiconductor devices using a sacrificial uniform vertical thickness spacer structure.
2. Description of the Related Art
Sidewall spacers provide many fundamental functions in semiconductor processing. For example, typically following gate structure formation, a source/drain extension implantation process is performed in order to form source/drain extension regions with relatively low doping levels immediately adjacent to a gate structure. Next, gate sidewall spacers are formed. These gate sidewall spacers subsequently function as masks (i.e., as shields) during a source/drain region implantation process. The source/drain region implant process forms source/drain regions with relatively high doping levels offset from the gate structure by the width of the gate sidewall spacers (i.e., aligned to the gate sidewall spacers). Such sidewall spacers may similarly be used as masks (i.e., as shields) during other process steps, including but not limited to, salicide formation and/or etch steps.
Sidewall spacers are conventionally formed by conformally depositing one or more layers of dielectric materials, such as an oxide (e.g., silicon dioxide) and/or a nitride (e.g., silicon nitride), to a desired thickness. However, the conformal deposition results in less material being deposited around the top corners of the gate structure, with rounding occurring. Then, an anisotropic etch process is performed to remove the dielectric material from the horizontal surfaces. As illustrated in FIG. 18, while the etch process is selected to be anisotropic, the resulting sidewall spacers 60 are inevitably tapered (i.e., not uniform) as a result of different deposition rates and etching rates near the upper and lower corners of the gate structure 20. That is, the thickness of the resulting sidewall spacers 60 is greater adjacent to the bottom surface of the gate structure closest to the substrate 10 (see first thickness 65) than it is adjacent to the top surface of the gate structure 20 (see second thickness 66).
As device sizes are scaled, achieving precise implant and/or etch profiles can be critical to achieving reliable electrical performance. For example, precise implant profiles can be critical for avoiding short channel effects, when implanting highly doped source/drain regions offset from the gate structure. Precise etch profiles can similarly be critical for avoiding such short channel effects, when etching trenches to be used for epitaxially grown source/drain regions offset from the gate structure. However, as a result of the tapered gate sidewall spacers, precise implant and/or etch profiles are difficult to achieve. That is, due to the tapered sidewall spacer structure, implant and/or etch profiles are inevitably graded. Such graded profiles can negatively impact device performance. Therefore, there is a need in the art for an improved method of forming planar and non-planar semiconductor devices using a uniform vertical thickness spacer structure in order to achieve precise implant and/or etch profiles and, thereby to optimize device performance.